Constant-gm circuit also known as beta-multiplier circuit is a widely used current reference generation circuit. And shown below in fig. 1 is the circuit diagram for a constant-gm circuit (not the complete diagram of functional constant-gm circuit, the start-up circuit is missing).

Fig 1. constant-gm bias circuit

The circuit is used for generating supply indepedent reference current such that the transconductance of the n-channel MOSFET M₁ (gm₁) tracks the 1/R_s or at least that is what we desire from this circuit when we are designing it. The theory and algebra for deriving currents and transconductances can be found in the textbooks by Prof Razavi and Prof Baker.

So what brings me here to write about this circuit? The circuit I drew above may be redrawn as shown below in the right half of the fig. 2 below, this circuit also looks like a constant-gm circuit. Under the same assumptions/approximations, the algebra for the derivation of currents and transconductances for the circuit in the left half is applicable to the circuit in the right half.

 

Fig. 2 Two possible configurations?

The question that I want to address here is - is the configuration of the constant-gm circuit shown in fig. 1 unique for this circuit? Or the configuration b) shown in the right half of the fig. 2 is also a viable configuration for this circuit? For some readers the answer to the question may be very obvious, so reading the rest of this blog is going to appear completely futile. 

If you don't know the answer, you may have already gathered that it is likely only one of these configuration works otherwise there is no sense in bringing up this question here. Now the question is which is the correct one? In the textbooks by Prof Razavi and Prof Baker the constant-gm circuit is drawn as the one shown in fig.1, so it is likely the configuration of fig. 1 is the correct one, which indeed is the case. 

Now the question is why does the other one not work? The answer to this question is somewhat subtle. This question had bothered me for sometime before I figured out the answer to the question. An easier way to find out the answer to the question would have been to just simulate the two configurations, it didn't occur to me do that before I figured out the answer and I performed the simulation to validate my understanding of why one works and the other one doesn't.

At this point, you may be thinking that you want to figure out the answer to the question yourself because you never considered this question before and in that case you may want to stop reading this blog now, and may want to come back later to see if you and me both have the same conclusion or maybe if you can't figure out the answer you will come back to get the answer.

Just in case you are not able to figure out the answer despite simulating and comparing the two configurations, don't be disheartened. It doesn't make you any less capable analog design engineer than those who were able to figure out the answer to this question. It is likely the way you understand and visualise the operation of circuits is different from others which doesn't render the answer to this question immediately obvious to you. To better understand what I mean to say here, I highly recommend watching these two videos of Richard Feynman explaining the different ways in which we think and visualise things.  

Now coming back to the circuits shown fig. 2, the circuit can be divided into two parts, one with PMOS network and the other with the NMOS network. In essence, the purpose of PMOS can be understood to provide current feedback with a factor of 1 i.e. the current sensed by the 'diode' transistor is produced by the other transistor in the same magnitude. This is also illustrated in the fig. 3 below.

Fig 3. PMOS half network in the constant-gm circuit.

The 2nd half of the circuit can be understood to be a current amplifying circuit. For the NMOS half of circuit in fig 2. a) redrawn in fig. 4, the gain is gm₂/gm₁ x 1/(1+gm₂R_s) and for the circuit in fig 2. b) redrawn in fig. 5, the gain is gm₁(1+gm₂R_s)/gm_2.

Fig. 4 NMOS half network for configuration a)

Fig. 5 NMOS half network for configuration b)

Now lets assume that a slight disturbance due to noise on the gate of transistor M1 in fig 4. and the gate of M2 in fig. 5 produces i_in extra current on top of the expected/desired bias current in the two branches. The output current i_out being generated because of the extra input current i_in is fed to the PMOS network, which feeds the current back into the gate of M1 in fig. 4 or the gate of M2 in fig. 5 with a factor of unity. Now there is some extra current on top of the already existing disturbance i_in, i_in now is i_in + i_extra which will produce i_extraout which in turn will be fed back to the gate of M1 or M2. i_in can be described by the following equation

i_additional = i_in + Gi_in +G²i_in + G³i_in + G⁴i_in + .... (summation of the terms of infinite geometric series and G is the current gain).

For i_additional to converge G has to be less than 1 otherwise i_in will grow to infinity, which is not possible in a real circuit. Instead of the current Iin growing to infinity the circuit is driven out of saturation to cause at least one of the two possibilities, either the current gain becomes less than 1 or the feedback factor of the PMOS network no longer unity or both conditions may result. Comparing the gains of the two configuration, it is pick the stable winner. The NMOS current amplifying network in the circuit shown in fig. 2 left half exhibits a current gain of gm₂/gm₁ x 1/(1+gm₂R_s) which is likely to be smaller than 1, because (1+gm₂R_s) is expected to be larger than gm₂/gm₁ (which lies between 1 ~ 2) the gain for the other configuration is inverse of this gain and hence it is likely to be greater than 1. Now we can easily pick which one out of the two configurations is a stable and working configuration. You can simulate these two configurations to check if the discussion given above holds true or not.

Here is a netlist that contains the two configurations which you can simulate using LTSPICE.

I have also included a graph from the SPICE results obtained from the LTSPICE simulation of the netlist and you can see that only one configuration gives stable supply independent current bias.

    

 

Cascode (shown in Fig. 1) is well known and widely used circuit for creating large-impedances in integrated circuits. Cascode circuits also provide another advantage i.e. isolation between input and output ports and thereby reducing the Miller-effect and as a result cascodes have a good frequency performance. And when impedances achieved from cascode circuits are not good enough, we go on to use active-cascodes or regulated-cascodes. Even though cascodes are affected by the limitations of headroom (voltage swing), there are work-arounds for this problem that have been figured out by designers (the smart engineers again). The question that I want to discuss here is - how did someone (must be a genius) think of this circuit which provides an elegant area-efficient solution for achieving large impedances consequently large voltage gains?

 

Fig 1. a) NMOS cascode sink b) regulated NMOS cascode sink. 

I think its highly unlikely that the engineers randomly tried putting transistors in series thinking that impedances add when we put them in series and discovered that in case of a constant current bias, the impedance actually gets magnified by the internal gain of the transistor stacked on top. Even if that was the case, the other question then to consider is - how did the smart design engineers figure out the idea of regulated-cascodes when they realized the impedance from cascode was not good enough?

I personally think there must have been a systematic engineering process behind developing such an idea, epiphany is unlikely, because fortunately or unfortunately epiphanies are few and far in between. And an engineering process involves solving a problem by breaking it into parts or smaller problems and layering the solutions of those smaller problems to create an intelligent and elegant solution to a broader/bigger problem. And that is why, for the development of new elegant idea/solution for a problem, requires the solutions to the smaller problems to exist. Anyhow, I am digressing from the topic of discussion, the philosophical issues are much better discussed in this terrific radiolab podcast. All readers are strongly encouraged to listen to it.     

Fig 2. a) source degeneration by a resistor b) source degeneration by active impedance of MOSFET M₂

Now coming back to the inception of cascode. Casode circuit is actually source degenerated circuit, just like the circuit shown in Fig 2. a). In the circuit shown in Fig 2. a) a resistor R_S source degenerates MOSFET M₁, while in cascode its the active impedance of a MOSFET (M₂ in Fig 2. b)) that acts like a degenerating resistor. We know that source degeneration improves the output impedance by a factor of (1 + g_mR_S), so larger the R_S, larger the impedance that can be achieved from a cascode. However, R_S can only be so large in an integrated circuit without increasing the area significantly, and one of the larger impedances available on integrated circuits is an active impedance of MOSFET biased in saturation, so degeneration using active impedance of MOSFET can easily provide higher gains in the output impedance at no significant cost of area. The fourth chapter on current sources, of the landmark text on analog circuits by professors Gray, Hurst, Lewis and Meyer, also implicitly suggests the same idea considering the way section discussing cascode is presented following the section discussing source degeneration.

Still how and why source degeneration? My guess is, source degeneration circuit was devised during the bipolar days. Unlike MOSFETs bipolar devices exhibit small input impedance and source degeneration improves both input impedance and output impedance by a factor of (1 + g_mR_S). The small-signal analysis and algebra illustrating that is given below.  

Fig 3. Small-signal equivalent of source degenerated bipolar transistor. 

Again the small-signal analysis only tells us why source degeneration helps or works, but not how would we think of it as the solution to the problem of small input and output impedances. In order to think of source degeneration as the solution to the problem of small input and output impedances, we need to think of source degeneration as series-series feedback. And this is not something explicitly apparent. Let me try to explain, if you can't see it already.  

Fig 4. MOS transconductance amplifier. 

The NMOS transistor M₂ in the circuits shown in Fig 1. can be looked upon as a transconductance amplifier with a current gain g_m (shown in Fig 4. above) with gate and source being positive and negative terminals respectively. One strange property of MOSFET transconductance amplifier is that the output current flows to ground through the negative terminal of the amplifier, it turns out to be really useful, as we will see later. 

Fig 5. series-series feedback loop as source degeneration.

The series-series feedback loop (shown in Fig. 5) can be constructed as resistor connected between the negative terminal of transconductance and ground, if the output current flows through the negative terminal of the transconductance amplifier. If we do that in the resulting circuit the output current gets sampled and converted into voltage using the degenerating resistor then fed to the amplifier at the negative terminal. Hence the result is series-series negative feedback. Series-series feedback increases both input and output impedances by a factor of (1 + g_mβ) ( ≈ (1 + g_mR_S), algebra given below). Note here β has the dimensions of an impedance(β = V_f/I_out). If we understand this, then we can use the series-series feedback to fulfill the need for higher input and output impedances at the expense of current gain ( g_m). This is the real ingenious idea behind source degeneration, consequently the cascode circuit i.e. transforming the series-series feedback loop to source degeneration circuit. Once we do that moving on to regulated-cascode circuit for even higher impedances is somewhat straight-forward, if you have been paying attention, you would have guessed it already. If you haven't, then let me explain.

Fig 6. series-series feedback 

  The feedback factor in the case of source degeneration is the degenerating impedance R_S (= V_f/I_out), so larger the feedback factor β larger the gain (1 + g_mβ ≈ 1 + g_mR_S) in output impedance. If we can't increase R_S beyond a certain value, we can start playing with V_f and I_out. The quantity being fed back in series-series feedback scheme is a voltage, and the nice thing about voltages is that they can be easily amplified. Now, if we break the series-series feedback loop after feedback element and put an amplifier (of gain A) as shown in Fig. 7, we can improve increase the feedback factor β by a factor of A and consequently increase output impedance by a factor A more.     

Fig 7. modifying the series-series feedback loop. 

However there is one minor problem if we do that in the source degeneration circuit, we can't sample the voltage at the source node and feed the amplified voltage back at the same node, it will put the voltage amplifier in a positive feedback loop (Fig. 8), however we also have the positive terminal of the transconductance amplifier to feed the voltage and we can change the gain from A to -A to achieve the same effect. If we do that we arrive at regulated-cascode/source degenerated circuit. The idea behind regulated-cascode is often described by need to ensure a almost constant drain bias at (D₁) drain of M₁ (Fig 1.) irrespective of the variation in the voltage at the drain of transistor M₂ and the feedback using amplifier ensures that, but that doesn't quite explain inception of regulated-cascode, it just explains why it works. And for that matter, in principle, even regular cascodes have the same basis. The idea behind the origins of regulated-cascode must have been series-series feedback.   

Fig 8. constructing the regulated-cascode.

I am guessing, the person who came up with the idea of regulated-cascode must have had a shared dream about Giants winning the World Series (please don't mind the bad joke).

 

Why do we perform small signal analysis, when we are analyzing or designing analog circuits? This is a fundamental question that I think, is not discussed rigorously enough in the classes or text books on analog circuit design. I will attempt to qualitatively address this question here in this blogpost.

 

Fig. 1 a) Small-signal MOSFET model and b) small-signal bipolar model

The way we derive the small signal models for transistors (shown in Fig. 1 a) and b) ) tells us something about the answer to the question i.e. by using the methods to describe transistors with their small-signal models, we can reduce the non-linear devices (like MOSFETs, bipolar transistors and diodes) to a circuit composed of linear elements. A circuit described by linear elements is much easier to analyze, also it provides us some handle to the circuit which we can use for the problem of design.

Moreover, we can't really perform a complete SPICE like analysis by hands on paper.

Another way to look at it, as professor Razavi has described in the third chapter of his widely studied textbook, even if the amplifier has a non-linear response, its response can be captured by a polynomial function in a certain signal range. For small-signals the polynomial response function reduces to a constant, in other words the response is linear. 

The answer I have provided above sounds pedantic and it also leads to another question -  how and why is small signal analysis valid? and why is it not just a method of abstraction for easier analysis? For example as shown in the Fig. 2 the signals applied between nodes A, B, C and ground are not necessarily small and they can in the order of volts or larger. So, is the small signal analysis valid for the amplifiers I, II and III? If yes, why?

 

Fig. 2 Typical use of amplifiers

The short answer to the second question is - yes and the reason is negative feedback. Another academic sounding answer. Allow me to me elaborate, and let us assume that the amplifiers I, II and III shown in Fig 2. are the well known single-ended two-stage CMOS amplifier shown in Fig. 3. The opamp (amplifier) doesn't necessarily have to be a two-stage CMOS amplifier, but more or less similar behavior is also demonstrated by the other amplifiers as well.  

Fig. 3  Two-stage CMOS amplifier    

 

Fig. 4 circuit from fig. 2 top left redrawn

Lets start with the circuit in Fig 2 top left, redrawn in Fig 4. I will assume that the resistors R₁ and R₂ are very large and equal for the sake of this discussion. The resistors R₁ and R₂ have to be large so that they don't draw too much current out of the 2nd stage of the amplifier (less than 10 % of 2nd-stage the bias current for λ_n,p ≤ 0.1 or V_{Early n,p} ≥ 10 V). Let me also assume that V_DD and V_SS are +3 V and -3V, respectively.  We now apply a signal (V_in) of 1 Volt at node A, as a result some current flows through R₁ and it will result in a voltage V_n at the negative terminal of the amplifier (the gate of transistor M2). If voltage V_n is positive, the voltage on node D1 will go up causing the transistor M6 to become less ON and resulting the output voltage of the amplifier to go low somewhere close to V_SS. Similarly if the voltage V_n is negative, the voltage on node D2 will go down causing the transistor to become more ON and resulting in the amplifier output to go up somewhere close to V_DD. Now in this particular case the voltage V_n can not be a negative voltage, as that will result in currents through R₁ and R₂ to flow into node n, which is not possible according to Kirchoff's current law. 

Since we don't know what the voltage at the input (V_n) looks like and if it is not a small signal it will tend to turn transistor M2 considerably more ON and almost turn M1 OFF, as a result the node D1 will be pulled high, close to V_DD rail. The transistor M6 will be close to being OFF and the output is likely to be V_SS rail. In that case the voltage at the node n, using the resistive divider equation, will be (V_in x R₂ + V_SS x R₁)/(R₂ + R₁) = (R x 1 + R x -3) / (R + R) = -2. Now, a negative voltage on n will tend to pull the output away from V_SS rail and thus, as we discussed earlier, it is not a possible stable voltage on the negative input terminal (node n). In fact, the voltage on the negative terminal of the amplifier has to be R₂/R₁ x V_in/A (algebra below)  

where A is the voltage gain of the amplifier (whatever that maybe). If every FET in the amplifier discussed above is operating in saturation the voltage gain A of the circuit will be large. So the voltage at node n will be a small number, so the input to the amplifier is a small voltage i.e. a small signal. 

Similarly, for the circuit of top right when a large positive voltage is applied on the positive terminal of the amplifier its output tends to swing up. The amplifier output continues to swing up to a level which is just below V_in, such that the difference between V_in and V_out is small enough to cause amplifier output to stop being pulled to the V_DD rail. In other words A(V_in - V_out) = V_out or V_out = V_in x (A / (1 + A)). Therefore the input voltage between two terminals of the amplifier V_in - V_out = V_in/(1 + A), when A is large (100 or larger is good enough in most cases) the signal seen by the amplifier is small.

For the circuit shown in bottom center of Fig. 2 redrawn in Fig. 5 below, when we apply a voltage V_in at node C, some charge q₁ develops on the top plate of capacitor C₁, now equivalent negative charge has to appear on the bottom plate of capacitor C₁. The charge developed on the bottom plate has to be balanced by a positive charge on the negative terminal (n) of the amplifier. A positive charge on the negative input of the amplifier will imply a positive voltage on the negative terminal and a positve voltage on the negative terminal of amplifier will cause the amplifier output to go low, towards V_SS rail. Now capacitor C₂ will start accumulating negative charge on the plate connected to the amplifier output, to balance that negative charge some positive charge (which was generated by the act of applying a voltage V_in on C₁, in first place) from the negative terminal of the amplifier will get transferred to bottom plate of capacitor C₂, until a stable voltage V_n develops on the negative terminal of the amplifier resulting in a stable output voltage V_out . Accoding to conservation of charge + q₁ on top plate of C₁ = - q₁ on the bottom plate of C₁, - q₁ gets balanced by total positive charge on bottom plate of C₂ and the negative terminal of the amplifier. q₁ = C₁(V_in - V_n) = - C₂(V_out - V_n) + C_p,amp  x V_n. C_p,amp is the parasitic capacitance at the negative terminal of the amplifier, also V_n = - V_out / A. Substituting in the equation we get V_out = - C₁ / ( C₂ + (C₁ + C₂ + C_p,amp) / A) x V_in ≈ - C₁ / C₂ x V_in for large A, therefore V_n = - C₁ / C₂ x V_in / A, which is small for large A.     

Fig. 5 redrawn switched capacitor circuit from Fig. 2

Small signals at input are all good, how about the signals at output? The output signals in all the circuits discussed above are not small, again. However, MOSFETs and BJTs both have an interesting property of linear current (I_D or I_C) vs voltage relationships (at the drain and collector terminals) for a very wide voltage range (voltages ~ supply voltages), when operated in saturation and forward active regions. This is illustrated in the Fig. 5 shown below. The small signal parameter r_o can practically capture the behavior of the devices for large voltage signals.

Fig. 6 I_D - V_D and I_C - V_C curves

All the circuits discussed above are using amplifier in a closed loop, however not all analog circuits are used in a closed loop, the signal for those circuits may not necessarily be small all the time. For circuits such as comparator, LNA, mixers or power amplifiers, the small signal analysis is not valid entirely, it is just an approximate engineering method used to simplify the analysis. In the case of RF circuits, the linearity is essentially simulated/estimated using the CAD tools and that is why qualifications for RF circuit design requires understanding of the limitations of simulators and models in estimating linearity and high frequency behavior of circuits in addition to all high-frequency circuit design theory.

This blog is intended for people starting to learn analog circuit design, however it still requires some familiarity with somewhat advanced (from a beginner's standpoint) analog circuits such as differential amplifiers. It becomes much easier to learn circuit design if we can understand how and why the methodologies for analyzing circuits are applicable to the actual circuits.

If you notice any mistake or have any suggestion for adding anything here, please email me at achal[ dot ]kathuria[ at ]gmail. I will sincerely appreciate any feedback.